Nano Lab

Details: Last Updated on Wednesday, 19 October 2016 18:31

Nano Lab

Research

Nanoelectronics Compact modelling of semiconductor devices, Development and support of BSIM model, SPICE modelling of High Voltage/Power semiconductor devices; DC,CV and RF characterization, atomistic simulation of Nanoscale devices

Nano Lab

Team

+ - Facilities Click to collapse

200mm wafer characterization facility: DC, CV and RF characterization of electron devices, for temperature range -65C to 200C.
Equipped with state of the art software tools:
SPICE simulators - HSPICE, SPECTRE, ADS
RF simulation and design - Agilent ADS and Microwave office
TCAD Simulators - Silvaco Atlas and Synopsys Sentaurus
Parameter Extraction tool - ICCAP
Atomistic Simulator - ATK Quantumwise, NanoMOS, NextNano
Multiprocessor Linux servers and workstations
Library with reference books and manuals along with projector, screen,whiteboard for discussions and group meetings
Network Printing, Scanning and Xeroxing

Features

+ - Publications Click to collapse

P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, A. Medury, C. Hu and Y. S. Chauhan, "BSIM-IMG: Compact Model for RF-SOI MOSFETs", accepted in IEEE Device Research Conference (DRC), Columbus, USA, June 2015.
S. A. Ahsan, S. Ghosh, K. Sharma, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling of a GaN HEMT with Gate and Source Field Plates", accepted in IEEE International Symposium on Compound Semiconductors, Compound Semiconductor Week, June-July 2015.
P. Rastogi, T. Dutta, S. Kumar, A. Agarwal, and Y. S. Chauhan, "First Principle Study of Quantization Effects on UTB InP MOSFET", accepted in IEEE International Symposium on Compound Semiconductors, Compound Semiconductor Week, June-July 2015.

A. Dasgupta and Y. S. Chauhan, "Surface Potential Based Modeling of Induced Gate Thermal Noise for HEMTs", accepted in IEEE International Symposium on Compound Semiconductors, Compound Semiconductor Week, June-July 2015.
S. Khandelwal, Y. S. Chauhan, B. Iniguez, and T. Fjeldly, "RF Large Signal Modeling of Gallium Nitride HEMTs with Surface-Potential Based ASM-HEMT Model", accepted in IEEE International Symposium on Compound Semiconductors, Compound Semiconductor Week, June-July 2015.
A. Dasgupta, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Compact model for GaN HEMTs", accepted in IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC2015), Singapore, June 2015.
K. Sharma, A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Effect of Access Region and Field Plate on Capacitance behavior of GaN HEMT", accepted in IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC2015), Singapore, June 2015.
H. Agarwal, C. Gupta, P. Kushwaha, C. Yadav, J. P. Duarte, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model", accepted in IEEE Journal of Electron Devices Society, 2015.
H. Agarwal, S. Khandelwal, S. Dey, C. Hu, and Y. S. Chauhan, "Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs", appearing in IEEE Journal of Electron Devices Society, 2015.
S. Khandelwal, J. P. Duarte, A. Medury, Y. S. Chauhan, and C. Hu, "New Industry Standard FinFET Compact Model for Future Technology Nodes", accepted in IEEE VLSI Technology symposium, Kyoto, June 2015.
S. Khandelwal, H. Agarwal, J. P. Duarte, K. Chan, S. Dey, Y. S. Chauhan, and C. Hu, "Modeling STI Edge Parasitic Current for Accurate Circuit Simulations", accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.
A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Surface potential based Modeling of Thermal Noise for HEMT circuit simulation", appearing in IEEE Microwave and Wireless Components Letters, 2015.
P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J. P. Duarte, C. Hu and, Y. S. Chauhan, "Modeling the Impact of Substrate Depletion in FDSOI MOSFETs", Solid State Electronics, Vol. 104, Issue 2, Feb. 2015.
S. Ghosh, A. Dasgupta, S. Khandelwal, S. Agnihotri, and Y. S. Chauhan, "Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs", IEEE Transactions on Electron Devices, Vol. 62, Issue 2, Feb. 2015
P. Rastogi, S. Kumar, S. Bhowmick, A. Agarwal and, Y. S. Chauhan, "Doping Strategies for Monolayer MoS2 via Surface Adsorption: A Systematic Study", ACS Journal of Physical Chemistry C, Vol. 118, Dec. 2014.
A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, " Compact Modeling of Flicker Noise in HEMTs ", IEEE Journal of Electron Devices Society, Vol. 2, Issue 6, Nov. 2014.
S. Ghosh, K. Sharma, S. Khandelwal, S. Agnihotri, T. A. Fjeldly, F. M. Yigletu, B. Iniguez, and Y. S. Chauhan, "Modeling of Temperature Effects in a Surface-Potential Based ASM-HEMT model", accepted in IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec. 2014.
P. Rastogi, S. Kumar, A. Agarwal, and Y. S. Chauhan, "Ab-initio study of doping versus adatom in monolayer MoS2", accepted in IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec. 2014.
A. Dasgupta, C. Yadav, P. Rastogi, A. Agarwal and Y. S. Chauhan, "Analysis and Modeling of Quantum Capacitance in III-V Transistors", accepted in IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec. 2014.
P. Kushwaha, C. Yadav, H. Agarwal, J. Srivatsava, S. Khandelwal, J. P. Duarte, C. Hu and Y. S. Chauhan, "BSIM-IMG with Improved Surface Potential Calculation Recipe", accepted in IEEE India Conference (INDICON), Pune, India, Dec. 2014.
C. Yadav, P. Kushwaha, H. Agarwal, Y. S. Chauhan, "Threshold Voltage Modeling of GaN Based Normally-Off Tri-gate Transistor", accepted in IEEE India Conference (INDICON), Pune, India, Dec. 2014.
H. Agarwal, Y. S. Chauhan, "Flicker Noise Modeling in BSIM6 Compact Model", MOS-AK Workshop, Venice, Italy, Sept. 2014.
Y. S. Chauhan, "Compact Modeling of FinFET and Ultra-Thin-Body devices", INUP Workshop on Compact Modeling, Bangalore, August 2014.
S. Khandelwal, J. P. Duarte, Y. S. Chauhan, and C. Hu, " Modeling 20nm Germanium FinFET with the Industry Standard FinFET Model ", IEEE Electron Device Letters, Vol. 35, Issue 7, July 2014.
Y. S. Chauhan, P. Kushwaha, S. Khandelwal, C. Yadav, N. Paydavosi, J. P. Duarte and C. Hu, "BSIMIMG: COMPACT MODEL FOR UTBBSOI MOSFETs", Workshop on Compact Modeling, Washington D.C., USA, June 2014. (Invited)
S. Khandelwal, J. P. Duarte, N. Paydavosi, Y. S. Chauhan, J. J. Gu, M. Si, P. D. Ye, and C. Hu, "InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG", Workshop on Compact Modeling, Washington D.C., USA, June 2014.
C. Yadav, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y. S. Chauhan, and C. Hu, " Modeling of GaN based Normally-off FinFET ", IEEE Electron Device Letters, Vol. 35, Issue 6, June 2014.
H. Agarwal, S. Khandelwal, Y. S. Chauhan, and C. Hu, "Noise Modeling in BSIM6 Compact Model", Workshop on Compact Modeling, Washington D.C., USA, June 2014.
C. Yadav, S. Khandelwal, and Y. S. Chauhan, "Modeling of AlGaN/GaN FinFET", Workshop on Compact Modeling, Washington D.C., USA, June 2014.
Y. S. Chauhan, "Semiconductor industry: CMOS technology and beyond", Motilal Nehru National Institute of Technology Allahabad, April 2014.
Y. S. Chauhan, S. Venugopalan, M.-A. Chalkiadaki, M. A. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad and C. Hu, " BSIM6: Analog and RF Compact Model for Bulk MOSFET", IEEE Transactions on Electron Devices, Vol. 61, Issue 2, Feb. 2014. (Invited)
A. Dutta, S. Sirohi, T. Ethirajan, H. Agarwal, Y. S. Chauhan, R. Q Williams, "BSIM6 - Benchmarking the Next Generation MOSFET Model for RF Applications", IEEE International Conference on VLSI Design, Mumbai, India, Jan. 2014.
J. R. Sahoo, H. Agarwal, C. Yadav, P. Kushwah, S. Khandewal, R. Gillon, Y. S. Chauhan, "High Voltage LDMOSFET Modeling using BSIM6 as Intrinsic-MOS Model", IEEE PrimeAsia, Visakhapatnam, Dec. 2013. (Gold Leaf Certificate)
S. Agnihotri, S. Ghosh, A. Dasgupta, S. Khandewal, Y. S. Chauhan, "A Surface Potential based Model for GaN HEMTs", IEEE PrimeAsia, Visakhapatnam, Dec. 2013. (Gold Leaf Certificate)
S. Khandelwal, C. Yadav, S. Agnihotri, Y. S. Chauhan, A. Curutchet, T. Zimmer, J.-C. Dejaeger, N. Defrance and T. A. Fjeldly, "A Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design", IEEE Transactions on Electron Devices, Vol. 60, Issue 10, Oct. 2013.
N. Paydavosi, S. Venugopalan, Y. S. Chauhan, J. P. Duarte, S. Jandhyala, A. M. Niknejad and C. Hu, "BSIM - SPICE Models Enable FinFET and UTB IC Designs", IEEE Access, 2013.
H. Agarwal, S. Venugopalan, M. Chalkiadaki, N. Paydavosi, J. P. Duarte, S. Agnihotri, C. Yadav, P. Kushwaha, Y. S. Chauhan, C. C. Enz, A. Niknejad and C. Hu, "Recent Enhancements in BSIM6 Bulk MOSFET Model", IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Glasgow, Scotland, Sept. 2013.
Y. S. Chauhan, S. Venugopalan, N. Paydavosi, P. Kushwaha, S. Jandhyala, J. P. Duarte, S. Agnihotri, C. Yadav, H. Agarwal, A. Niknejad and C. Hu, "BSIM Compact MOSFET Models for SPICE Simulation", IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Gdynia, Poland, June 2013. (Invited)
Y. S. Chauhan, "Industry Standard SPICE Modeling", Solid State Physics Laboratory (SSPL) - DRDO, Delhi, June 2013.
S. Khandelwal, S. Sharma, Y. S. Chauhan, T. Gneiting and T. A. Fjeldly, "Modeling and Simulation Methodology for SOA Aware Circuit Design in DC and Pulsed-Mode Operation of HV MOSFETs", IEEE Transactions on Electron Devices, Vol. 60, Issue 2, Feb. 2013.
Y. S. Chauhan, M. Chalkiadaki, S. Venugopalan, M. A. Karim, N. Paydavosi, S. Jandhyala, J. P. Duarte, C. Enz, A. Niknejad, C. Hu, "Global Geometrical Scaling in BSIM6", MOS-AK Workshop, San Francisco, Dec. 2012.
S. Khandelwal, Y. S. Chauhan, T. A. Fjeldly, "Analytical Modeling of Surface-Potential and Intrinsic Charges in AlGaN/GaN HEMT Devices", IEEE Transactions on Electron Devices, Vol 59, Issue 8, Oct. 2012.
Y. S. Chauhan, R. Gillon, M. Declercq, A. M. Ionescu, "Impact of Lateral Nonuniform Doping and Hot Carrier Injection on Capacitance Behavior of High Voltage MOSFETs", IETE Technical Review, Vol. 25, Issue 5, pp. 244-250, Sept.-Oct 2008.
M. A. Karim, Y. S. Chauhan, S. Venugopalan, A. B. Sachid, D. D. Lu, B.-Y. Nguyen, O. Faynot, A. M. Niknejad and C. C. Hu, "Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs", IEEE Electron Device Letters, Vol. 33, No. 9, Sept. 2012.
M.-A. Chalkiadaki, A. Mangla, C. C. Enz, Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Niknejad, C. Hu, "Evaluation of the BSIM6 Compact MOSFET Modelʹs Scalability in 40nm CMOS Technology", IEEE European Solid-State Device Research Conference, Bordeaux, France, Sept. 2012.
Y. S. Chauhan, S. Venugopalan, M. A. Karim, S. Khandelwal, N. Paydavosi, P. Thakur, A. M. Niknejad and C. C. Hu, "BSIM - Industry Standard Compact MOSFET Models", IEEE European Solid-State Device Research Conference, Bordeaux, France, Sept. 2012. (Invited)
Y. S. Chauhan, M. A. Karim, A. Niknejad, C. Hu, "Thermal Network Extraction in Ultra-Thin-Body SOI MOSFETs", MOS-AK Workshop, Bordeaux, France, Sept. 2012.
S. Khandelwal, Y. S. Chauhan, D. D. Lu, S. Venugopalan, M. A. Karim, A. B. Sachid, B.-Y. Nguyen, O. Rozeau, O. Faynot, A. M. Niknejad and C. C. Hu, "BSIM-IMG: A Compact Model for Ultra-Thin Body SOI MOSFETs with Back-Gate Control", IEEE Transactions on Electron Devices, Vol. 59, Issue 8, pp. 2019-2026, Aug. 2012