Publications

Research output by year and type

Books

Industry Standard FDSOI Compact Model BSIM-IMG For IC Design (Sept. 2018)
Authors: Sourabh Khandelwal, Chenming Hu, Yogesh Singh Chauhan, Thomas Mckay, Juan Pablo Duarte, Pragya Kushwaha, Harshit Agarwal
FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard
Authors: Yogesh S. Chauhan, Darsen Lu, Sriram Venugopalan, Sourabh Khandelwal, Juan P. Duarte, Navid Paydavosi, Ali M. Niknejad, and Chenming Hu
POWER/HVMOS Devices Compact Modelling (contributed a chapter)
Editors: Wladyslaw Grabinski and Thomas Gneiting

Publications

2022
  • Journal Articles:
  • 1 A. Priydarshi, Y. S. Chauhan, S. Bhowmick, and A. Agarwal, "Strain-tunable in-plane ferroelectricity and lateral tunnel junction in monolayer group-IV monochalcogenides", under revision in Journal of Applied Physics, 2022.
  • 2 K. Nandan, B. Ghosh, A. Agarwal, S. Bhowmick and Y. S. Chauhan, "Two-dimensional MoSi2N4: An Excellent 2D Semiconductor for Field-Effect Transistors", IEEE Transactions on Electron Devices, 2022.
  • 3 D. Rajasekharan, N. Rangarajan, S. Patnaik, O. Sinanoglu, and Y. S. Chauhan, "SCANet: Securing the Weights with Superparamagnetic-MTJ Crossbar Array Networks", IEEE Transactions on Neural Networks and Learning Systems, 2022.
  • 4 S. Salamin, G. Zervakis, F. Klemme, H. Kattan, Y. S. Chauhan, J. Henkel, and H. Amrouch, "Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU", IEEE Transactions on Computers, 2022.
  • 5 D. Rajasekharan, A. Gaidhane, A. R. Trivedi, and Y. S. Chauhan, "Ferroelectric FET-based Implementation of FitzHugh-Nagumo Neuron Model", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022.
  • Conference Papers:
  • 1 Y. S. Chauhan, A. Pampori, R. Dangi, P. Kushwaha, E. Yadav, S. Sinha, "A Turnkey Large-Signal Model for Amplifier Design in 5G Spectra using AlGaN/GaN HEMTs", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Oita, Japan, Mar. 2022.
2021
2020
2019
2018
2017
2016
2015
  • Journal Articles:
  • 1 C. Yadav, J. P. Duarte, S. Khandelwal, A. Agarwal, C. Hu, and Y. S. Chauhan, "Capacitance Modeling in III-V FinFETs", IEEE Transactions on Electron Devices, Vol. 62, Issue 11, Nov. 2015.
  • 2 P. Rastogi, T. Dutta, S. Kumar, A. Agarwal, Y. S. Chauhan, "Quantum Confinement Effects in Extremely Thin Body Germanium n-MOSFETs", IEEE Transactions on Electron Devices, Vol. 62, Issue 11, Nov. 2015.
  • 3 S. Khandelwal, H. Agarwal, J. P. Duarte, K. Chan, S. Dey, Y. S. Chauhan, and C. Hu, "Modeling STI Edge Parasitic Current for Accurate Circuit Simulations", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 8, Aug. 2015.
  • 4 S. Khandelwal, J. P. Duarte, A. Medury, Y. S. Chauhan, S. Salahuddin, and C. Hu, "Modeling SiGe FinFETs with Thin Fin and Current Dependent Source/Drain Resistance", IEEE Electron Device Letters, Vol. 36, Issue 7, July 2015.
  • 5 A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Surface potential based Modeling of Thermal Noise for HEMT circuit simulation", IEEE Microwave and Wireless Components Letters, Vol. 25, Issue 6, June 2015.
  • 6 H. Agarwal, S. Khandelwal, S. Dey, C. Hu, and Y. S. Chauhan, "Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs", IEEE Journal of Electron Devices Society, Vol. 3, Issue 4, April 2015.
  • 7 H. Agarwal, C. Gupta, P. Kushwaha, C. Yadav, J. P. Duarte, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model", IEEE Journal of the Electron Devices Society, Vol. 3, Issue 3, March 2015.
  • 8 P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J. P. Duarte, C. Hu, and Y. S. Chauhan, "Modeling the Impact of Substrate Depletion in FDSOI MOSFETs", Solid State Electronics, Vol. 104, Issue 2, Feb. 2015.
  • 9 S. Ghosh, A. Dasgupta, S. Khandelwal, S. Agnihotri, and Y. S. Chauhan, "Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs", IEEE Transactions on Electron Devices, Vol. 62, Issue 2, Feb. 2015.
  • Conference Papers:
  • 1 S. Agnihotri, S. Ghosh, A. Dasgupta, A. Ahsan, S. Khandewal, and Y. S. Chauhan, "Modeling of Trapping Effects in GaN HEMTs", IEEE India Conference (INDICON), New Delhi, India, Dec. 2015.
  • 2 C. Gupta, H. Agarwal, Akira Ito, S. Ghosh, P. Khushwaha, C. Hu, and Y. S. Chauhan, "Modeling of Zero-Vth MOSFET with Industry Standard BSIM6 Model", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 3 G. Pahwa, A. Agarwal, and Y. S. Chauhan, "Compact Modeling of Negative Capacitance Transistor with Experimental Validation", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 4 C. Yadav, A. Agarwal, and Y. S. Chauhan, "Compact Modeling of Charge Density and Capacitance in III-V channel Double Gate FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 5 A. Dasgupta, A. Agarwal, and Y. S. Chauhan, "Compact Model for charge centroid in III-V FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 6 S. Ghosh, S. Agnihotri, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Analysis and Modeling of Trapping Effects in RF GaN HEMTs under Pulsed Conditions", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 7 S. Agnihotri, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Impact of Gate Field Plate on DC, C-V, and Transient Characteristics of Gallium Nitride HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 8 K. Sharma, S. Ghosh, A. Dasgupta, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Capacitance Analysis of Field Plated GaN HEMT", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 9 A. Dasgupta, A. Agarwal, and Y. S. Chauhan, "Compact Modeling of Quasi-Ballistic transport in FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 10 Y. Sahu, P. Kushwaha, J. P. Duarte, S. Khandelwal, C. Hu and Y. S. Chauhan, "Compact Modelling of Drain Current Thermal Noise in FDSOI MOSFETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 11 P. Kushwaha, S. Khandelwal, C. Hu and Y. S. Chauhan, "Recent Updates in Industry Standard BSIM-IMG Model for FDSOI Transistors", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 12 T. Dutta, M. Agrawal, A. Agarwal and Y. S. Chauhan, "Wavefunction Penetration Effects in Extremely Scaled III-V MOSFETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 13 N. Mohamed, H. Agarwal, C. Gupta, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Scaling Capabilities of Industry-Standard BSIM6 MOSFET Model", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 14 H. Agarwal, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Analysis and Modeling of Assymetric Channel MOSFET", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 15 S. A. Ahsan, S. Ghosh, J. Bandarupalli, S. Khandelwal, and Y. S. Chauhan, "Physics based large signal modeling for RF performance of GaN HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 16 P. Rastogi, A. Agarwal, S. Bhowmick, and Y. S. Chauhan, "Doping Behavior via Adsorption in Monolayer Black Phosphorous", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  • 17 S. Khandelwal, S. Ghosh, Y. S. Chauhan, B. Iniguez, T. A. Fjeldly and C. Hu, "Surface-Potential-Based RF Large Signal Model for Gallium Nitride HEMTs", IEEE Compound Semiconductor IC Symposium (CSICS), New Orleans, USA, Oct. 2015.
  • 18 B. K. Kompala, P. Kushwaha, S. Khandelwal, J. P. Duarte, A. Medury, C. Hu, and Y. S. Chauhan, "Modeling of Nonlinear Thermal Resistance in FinFET", International Conference on Solid State Devices and Materials (SSDM2015), Sapporo, Japan, September 2015.
  • 19 J. P. Duarte, S. Khandelwal, A. Medury, C. Hu, P. Kushwaha, H. Agarwal, A. Dasgupta, and Y. S. Chauhan "BSIM-CMG: Standard FinFET Compact Model for Advanced Circuit Design", IEEE European Solid-State Circuit Conference (ESSCIRC), Graz, Austria, Sept. 2015. (Invited)
  • 20 P. Rastogi, T. Dutta, S. Kumar, A. Agarwal, Y. S. Chauhan, "Confinement Effects on Germanium Band-structure for UTB MOSFET", SRC TECHCON, Austin, USA, September 2015.
  • 21 P. Kushwaha, J. P. Duarte, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Thermal Resistance Scaling with Number of fins in FinFET", SRC TECHCON, Austin, USA, September 2015.
  • 22 C. Yadav, A. Agarwal, Y. S. Chauhan, "Simulation study of gate capacitance with back bias effects in III-V UTB devices", SRC TECHCON, Austin, USA, September 2015.
  • 23 P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, A. Medury, C. Hu and Y. S. Chauhan, "BSIM-IMG: Compact Model for RF-SOI MOSFETs", IEEE Device Research Conference (DRC), Columbus, USA, June 2015.
  • 24 S. A. Ahsan, S. Ghosh, K. Sharma, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling of a GaN HEMT with Gate and Source Field Plates", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015.
  • 25 A. Dasgupta and Y. S. Chauhan, "Surface Potential Based Modeling of Induced Gate Thermal Noise for HEMTs", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015.
  • 26 S. Khandelwal, Y. S. Chauhan, B. Iniguez, and T. Fjeldly, "RF Large Signal Modeling of Gallium Nitride HEMTs with Surface-Potential Based ASM-HEMT Model", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015. (Invited)
  • 27 P. Rastogi, T. Dutta, S. Kumar, A. Agarwal, and Y. S. Chauhan, "First Principle Study of Quantization Effects on UTB InP MOSFET", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015.
  • 28 A. Dasgupta, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Compact model for GaN HEMTs", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, June 2015.
  • 29 K. Sharma, A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Effect of Access Region and Field Plate on Capacitance behavior of GaN HEMT", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, June 2015.
  • 30 S. Khandelwal, J. P. Duarte, A. Medury, Y. S. Chauhan, and C. Hu, "New Industry Standard FinFET Compact Model for Future Technology Nodes", IEEE VLSI Technology symposium, Kyoto, June 2015.
2014
2013
2012
2011
2010
2008
2007
2006
2005
2003
  • Conference Papers:
  • 1 B. Mazhari, and Y. S. Chauhan, "Design of current-Programmed amorphous-Silicon AMOLED Pixel Circuit", The 8th Asian Symposium on Information Display, China, 2003.
  • 2 B. Mazhari, and Y. S. Chauhan, "A New Negative Feedback based poly-Silicon AMOLED Pixel Circuit with Highly Linear Transfer Characteristics", 10th International Display Workshop, Fukuoka, Japan, 2003.