Dr. Yogesh Singh Chauhan is a full professor in the Department of Electrical Engineering at IIT Kanpur and an IEEE Fellow. Prof. Chauhan at IIT Kanpur develops industry standard compact models for state-of-the-art nanoscale Silicon, Gallium Nitride, 2D material and ferroelectric negative capacitance transistors, that are used by the semiconductor companies worldwide. He is carrying out research on compact modeling (ASM-HEMT, BSIM-BULK, BSIM-CMG, BSIM-IMG, BSIM4, BSIM-SOI etc.), RF circuit design, Brain-inspired computing, atomistic simulation and characterization of semiconductor devices. His work is being used to design integrated circuits (IC) for mobile phones, computers, 5G communication, defense and space applications etc.
Prof. Chauhan did his B.E. from Shri Govindram Seksaria Institute of Technology and Science Indore, India in 2001 followed by an M.Tech. in Microelectronics and VLSI from IIT Kanpur in 2003. He went on to earn his doctorate from Switzerland in 2007, and started his career as an Associate Design Engineer at ST Microelectronics in Noida, India in 2003. He then served as a Manager of Modeling, Physical Design, Design Automation in Semiconductor Research and Development Center at IBM, Bangalore, India from 2007 to 2010 and as a Senior Engineer at Tokyo Institute of Technology from March 2010 to July 2010 where he worked on Modeling and Simulation of Nanoelectromechanical FET. Prof. Chauhan did his Post-Doctoral studies from University of California, Berkeley and later joined IIT Kanpur as an Assistant Professor in 2012.
