2025
M. A. Bhat and I. Mondal, "A Frequency-Translated, 1-to-5GHz Centred, All-Passive, Programmable-Bandwidth, Switched-Capacitor Delay-Line with 6.5-to-8.2dB Delay-Independent Insertion Loss in 65nm CMOS," to appear in proc. of IEEE Solid State Circuits Conference (ISSCC) 2026.
U. Maurya, M. Arrawatia and N. Nallam, "A Low-Loss T/R Module With Balanced Power Amplifier for High Antenna Impedance Tolerance," in IEEE Open Journal of Circuits and Systems, vol. 6, pp. 414-423, 2025. Link
Sameer Kumar and Imon Mondal, “Design and Analysis of a Source Parasitic Insensitive Fully-passive N-path Receiver with sub-3dB NF,” in IEEE Journal of Solid-State Circuits. Link
M. A. Bhat and I. Mondal, "A 3–5.5 GHz Compact, Power-Efficient, Switched LC Delay-Line With 0.2–1.1 ns Delay Range," in IEEE Journal of Solid-State Circuits. Link
R. S. A. Kumar, "Using the Miller Theorem in LPTV Networks to Analyze Miller N-Path Filters," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025, pp. 1-5. LInk
M. A. Bhat and I. Mondal, "An LPTV Programmable Bandpass True-time-delay Line Without External Clock-phase Shifter," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025, pp. 1-5. Link
2024
R. S. Ashwin Kumar, "Analysis of Stability, Noise, and Design Guidelines for a Cascaded Floating-Inverter Amplifier," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 9, pp. 4126-4130, Sept. 2024. Link
N. Rakesh and R. S. A. Kumar, "Low Noise Low Power Readout Circuit For Capacitance Based MEMS Accelerometers," 2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Taipei, Taiwan, 2024, pp. 100-104. Link
R. S. Ashwin Kumar, "Flip-Around Level-Shifting For Switched-Capacitor Amplifiers to Improve the Closed-Loop Settling of Floating-Inverter Amplifiers," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5. (Won 2nd best paper award in ISCAS 2024). Link
2023
M. A. Bhat and I. Mondal, "A Low-Loss, Compact Wideband True-Time-Delay Line for Sub-6GHz Applications Using N - Path Filters," 2023 IEEE Asia Pacific Conference on Circuits and Systems, Hyderabad, India, 2023 pp. 149-153. Link
M. Anupam and I. Mondal, "A Robust Overdesign Prevention Circuit Technique Under Widely Varying Ambient Conditions," 2023 IEEE Asia Pacific Conference on Circuits and Systems, Hyderabad, India, 2023, pp. 280-284. Link
Abhishek Kumar, Shubham Sahay and Imon Mondal, “An Automatic Leakage Compensation Technique for Capacitively Coupled class-AB Operational Amplifiers,” IEEE International Symposium on Circuits and Systems 2023. Link
2022
R. S. Ashwin Kumar, N. Krishnapura, and P. Banerjee, "Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier," IEEE Journal of Solid-State Circuits, vol. 57, no. 11, pp. 3384-3395, Nov. 2022. Link
J. Kaur, S. Saurabh, and S. Sahay, "Muller C-Element Exploiting Programmable Metallization Cell for Bayesian Inference," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, no. 4, pp. 750-761, Dec. 2022. Link
S. Pal, S. Sahay, W. -H. Ki and C. -Y. Tsui, "A 10T Soft-Error-Immune SRAM With Multi-Node Upset Recovery for Low-Power Space Applications," in IEEE Transactions on Device and Materials Reliability, vol. 22, no. 1, pp. 85-88, March 2022. Link
M. Anupam, H. Rathore and I. Mondal, "Bandwidth-enhanced Feed-forward Amplifier with Shared Class-AB Gain and Compensation Paths," 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 2943-2947. Link
R. S. Ashwin Kumar, "Using the Miller Theorem to Analyze Two-Stage Miller-Compensated Opamps," 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 2938-2942. Link
2021
R. S. A. Kumar and N. Krishnapura, "Multi-Channel Analog-to-Digital Conversion Using a Delta-Sigma Modulator Without Reset and a Modulated-Sinc-Sum Filter," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 1, pp. 186-195, Jan. 2022. Link
N. Bajpai, A. Pampori, P. Maity, M. Shah, A. Das, and Y. S. Chauhan, "A Low Noise Power Amplifier MMIC to Mitigate Co-site Interference in 5G Front End Modules", IEEE Access, Vol. 9, pp. 124900-124909, Sept. 2021. Link
Chithra, A. Narayanan, R. S. Ashwin Kumar and N. Krishnapura, "Auto-zeroing Static Phase Offset in DLLs using a Digitally Programmable Sensing Circuit", IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 68, no. 6, pp. 1788-1792, June 2021. Link
Imon Mondal and Nagendra Krishnapura, “Effects of AC Response Imperfections in True-Time-Delay Lines,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS II), vol. 68, no. 4, pp. 1173-1177, April 2021. Link
R. S. Ashwin Kumar, "A Discrete-Time Delta-Sigma Modulator With Relaxed Driving Requirements And Improved Anti-Aliasing", IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-5. Link
H. Rathore and I. Mondal, "Breaking the Trade-Off between Bandwidth and Close-in Blocker Attenuation in an N-Path Filter," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-5. Link
Chithra, “A technique for measuring picosecond delays using phase modulation”, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-5 . Link
2020
R. S. Ashwin Kumar and N. Krishnapura, "Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-time Delta-Sigma Modulator Without Reset," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 67, no. 11, pp. 3693-3703, Nov. 2020. Link
Chithra and N. Krishnapura, “A flexible 18-channel multi-hit time-to-digital converter for trigger-based data acquisition systems,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 6, pp. 1892-1901, Jun. 2020. Link
Shubham Sahay, M. Bavandpour, M. R. Mahmoodi and Dmitri Strukov, "Energy-Efficient Moderate Precision Time-Domain Mixed-Signal Vector-by-Matrix Multiplier Exploiting 1T-1R Array", IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 6, no. 1, pp. 18-26, June 2020. Link
M. Bavandpour, Shubham Sahay, M. R. Mahmoodi and Dmitri Strukov, "Efficient Mixed-Signal Neurocomputing Via Successive Integration and Division", IEEE Transactions on VLSI systems, vol. 28, no. 3, pp. 823-827, Mar. 2020. Link
Imon Mondal, “Analysis and comparison of distortion of Miller and feed-forward opamps in negative feedback,” 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain, 2020, pp. 1-5. Link
2019
R. S. Ashwin Kumar and N. Krishnapura, "A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset and a Modulated-Sinc-Sum Filter", IEEE 45th European Solid-State Circuits Conference (ESSCIRC) , Cracow, Poland, 2019, pp. 365-368 . Link
Chithra and N. Krishnapura, “Static phase offset reduction technique for delay locked loops,” IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. Link
Imon Mondal, “Effect of circuit non-idealities on active on-chip delay lines,” IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Sapporo, Japan, pp. 1-5, May 2019. Link
Chithra and N. Krishnapura, “Modeling techniques for faster verification of a time-to-digital converter system-on-chip design,” IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India), Hyderabad, India, 2019, pp. 1-6. Link
2018 & Before
R. S. Ashwin Kumar, D. Behera and N. Krishnapura, "Reset-Free Memoryless Delta–Sigma Analog-to-Digital Conversion," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 65, no. 11, pp. 3651-3661, Nov. 2018. Link
Imon Mondal and Nagendra Krishnapura, “Expansion and compression of analog pulses using bandwidth switching of continuous-time filters,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol 65, pp. 2703-2714, Feb. 2018. Link
Imon Mondal and Nagendra Krishnapura, “Linearity and gain enhanced wideband transconductor using digitally auto-tuned negative conductance load.” IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Florence, Italy, pp. 1-5, 27-30 May 2018. Link
Imon Mondal and Nagendra Krishnapura, “A 2 GHz bandwidth, 0.25-1.7 ns true-time-delay element using a variable-order all-pass filter architecture in 0.13 μm CMOS,” IEEE Journal of Solid-State Circuits (IEEE JSSC), vol. 52, no. 8, pp. 2180-2193, Aug. 2017. Link
R. S. Ashwin Kumar, D. Behera and N. Krishnapura, "A Low Power Multi-Channel Input Delta-Sigma ADC Without Reset,” IEEE International Conference on VLSI Design and International Conference on Embedded Systems (VLSID), Hyderabad, India, 2017, pp. 9-14 . Link
Imon Mondal and Nagendra Krishnapura, “Gain enhanced high frequency OTA with on-chip tuned negative conductance load,” IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Lisbon, Portugal, pp. 2085-2088, 20-23 May 2015. Link
Imon Mondal and Nagendra Krishnapura, “Accurate constant transconductance generation without off-chip components,” 28th International Conference on VLSI Design, Bangalore, India, Jan. 2015, pp. 249-253. Link
Patents filed
Imon Mondal and Nagendra Krishnapura, "Tunable true-time-delay element using a variable order all-pass filter,'' India patent no. 511139
Chithra, A Narayanan, R. S. Ashwin Kumar, and N. Krishnapura, “Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit”, Patent no. 501606.
R. S. Ashwin Kumar and Nagendra Krishnapura, "Multi-Channel ADC Realization Using a Delta-Sigma Modulator Without Reset And a Modulated Sinc-Sum Filter", India patent application, Patent no. 495533.